scas334a ? december 1992 ? revised november 1995 1 post office box 655303 ? dallas, texas 75265 post office box 1443 ? houston, texas 77251?1443 low output skew for clock-distribution and clock-generation applications ttl-compatible inputs and outputs distributes one clock input to six clock outputs polarity control selects true or complementary outputs distributed v cc and gnd pins reduce switching noise high-drive outputs (?48-ma i oh , 48-ma i ol ) state-of-the-art epic- ? b ? bicmos design significantly reduces power dissipation packaged in plastic small-outline package description the cdc391 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. through the use of the polarity-control (t /c) inputs, various combinations of true and complementary outputs can be obtained. the output-enable (oe ) input is provided to disable the outputs to a high-impedance state. the cdc391 is characterized for operation from ? 40 c to 85 c. function table inputs output oe t /c a output y h x x z l ll l l lh h l hl h l h h l copyright ? 1995, texas instruments incorporated epic- ? b is a trademark of texas instruments incorporated. d package (top view) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd 1y2 1y3 gnd 2y1 2y2 gnd 3y1 1y1 1t /c v cc 2t /c a v cc 3t /c oe please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
scas334a ? december 1992 ? revised november 1995 2 post office box 655303 ? dallas, texas 75265 post office box 1443 ? houston, texas 77251?1443 logic symbol ? 1y1 16 1 1y2 2 1 1y3 3 1 2y1 5 2 2y2 6 2 3y1 8 3 1t /c 2t /c 3t /c en 9 12 a n1 15 n2 13 n3 10 oe ? this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. logic diagram (positive logic) 1y1 1y2 1y3 2y1 2y2 3y1 16 2 3 5 6 8 15 13 12 10 1t /c a 2t /c 3t /c oe 9
scas334a ? december 1992 ? revised november 1995 3 post office box 655303 ? dallas, texas 75265 post office box 1443 ? houston, texas 77251?1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ?0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) ?0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high state or power-off state, v o ?0.5 v to v cc + 0.5 v . . . . . . . current into any output in the low state, i o 96 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) ?18 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) ?50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum power dissipation at t a = 55 c (in still air) (see note 2) 0.77 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observe d. 2. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 300 mils. for more information, refer to the package thermal considerations application note in the 1994 abt advanced bicmos t echnology data book , literature number scbd002b. recommended operating conditions (see note 3) min nom max unit v cc supply voltage 4.75 5 5.25 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v v i input voltage 0 v cc v i oh high-level output current ?48 ma i ol low-level output current 48 ma ? t/ ? v input transition rise or fall rate 5 ns / v f clock input clock frequency 100 mhz t a operating free-air temperature ?40 85 c note 3: unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ ? max unit v ik v cc = 4.75 v, i i = ?18 ma ?1.2 v v oh v cc = 4.75 v, i oh = ? 48 ma 2 v v ol v cc = 4.75 v, i ol = 48 ma 0.5 v i i v cc = 5.25 v, v i = v cc or gnd 1 a i oz v cc = 5.25 v, v o = v cc or gnd 50 a i o v cc = 5.25 v, v o = 2.5 v ?15 ?100 ma v cc = 5.25 v, i o = 0, outputs high 10 i cc v cc = 5.25 v, i o = 0, v i = v cc or gnd outputs low 40 ma i cc v i = v cc or gnd outputs disabled 10 ma c i v i = 2.5 v or 0.5 v 3 pf c o v o = 2.5 v or 0.5 v 5 pf ? all typical values are at v cc = 5 v, t a = 25 c. not more than one output should be tested at a time, and the duration of the test should not exceed one second.
scas334a ? december 1992 ? revised november 1995 4 post office box 655303 ? dallas, texas 75265 post office box 1443 ? houston, texas 77251?1443 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see figures 1 and 2) parameter from (input) to (output) min max unit t plh a any y 1.5 5 ns t phl a any y 1.5 5 ns t plh t /c any y 1.5 5 ns t phl t /c any y 1.5 5 ns t pzh oe any y 1.5 5 ns t pzl oe any y 3 7 ns t phz oe any y 5 ns t plz oe any y 5 ns t sk(o) a any y (same phase) 0.5 ns t sk(o) a any y (any phase) 1 ns t sk(p) a any y 1 ns t r 1.5 ns t f 1.5 ns
scas334a ? december 1992 ? revised november 1995 5 post office box 655303 ? dallas, texas 75265 post office box 1443 ? houston, texas 77251?1443 parameter measurement information from output under test c l = 50 pf (see note a) load circuit for outputs s1 7 v open gnd 500 ? 500 ? test t plh /t phl t plz /t pzl t phz /t pzh s1 open 7 v open output control (low-level enabling) output waveform 1 s1 at 7 v (see note b) output waveform 2 s1 at open (see note b) v ol v oh t pzl t pzh t plz t phz 1.5 v 1.5 v 3.5 v 0 v 1.5 v v ol + 0.3 v 1.5 v v oh ? 0.3 v 0 v 3 v voltage waveforms propagation delay times voltage waveforms enable and disable times t plh t phl output 1.5 v 1.5 v 3 v 0 v 1.5 v v oh v ol input 0.8 v 2 v t f 0.8 v 2 v t r notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r 2.5 ns, t f 2.5 ns. d. the outputs are measured one at a time with one transition per measurement. figure 1. load circuit and voltage waveforms
scas334a ? december 1992 ? revised november 1995 6 post office box 655303 ? dallas, texas 75265 post office box 1443 ? houston, texas 77251?1443 parameter measurement information t plh1 2y2 2y1 2t /c 1y2 1y1 1t /c a t phl1 t plh5 t phl5 t plh2 t phl2 t plh6 t phl6 t plh3 t phl3 t phl7 t plh7 t plh4 t phl4 t phl8 t plh8 notes: a. output skew, t sk(o), from a to any y (same phase), can be measured only between outputs for which the respective polarity-control inputs (t /c) are at the same logic level. it is calculated as the greater of: ? the difference between the fastest and slowest of t plh from a to any y (e.g., t plhn , n = 1 to 4; or t plhn , n = 5 to 6) ? the difference between the fastest and slowest of t phl from a to any y (e.g., t phln , n = 1 to 4; or t phln , n = 5 to 6) ? the difference between the fastest and slowest of t plh from a to any y (e.g., t plhn , n = 7 to 8) ? the difference between the fastest and slowest of t phl from a to any y (e.g., t phln , n = 7 to 8) b. output skew, t sk(o), from a to any y (any phase), can be measured between outputs for which the respective polarity-control inputs (t /c) are at the same or different logic levels. it is calculated as the greater of: ? the difference between the fastest and slowest of t plh from a to any y or t phl from a to any y (e.g., t plhn , n = 1 to 4; or t plhn , n = 5 to 6, and t phln , n = 7 to 8) ? the difference between the fastest and slowest of t phl from a to any y or t plh from a to any y (e.g., t phln , n = 1 to 4; or t phln , n = 5 to 6, and t plhn , n = 7 to 8) figure 2. waveforms for calculation of t sk(o)
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